Abstract
Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004 (ref. 1), a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 (ref. 2) microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects.
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Data availability
The data that generated the waveforms in the test and validation is available from the corresponding author upon request.
Code availability
The code of the three test programs to validate PlasticARM is available from the corresponding author upon request.
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Authors and Affiliations
Contributions
J.B. and J.M. conceived the PlasticARM concept. S.C. designed the Cortex-M processor and J.B., J.M. and J.K. implemented the SoC. J.K. developed the PlasticARM test framework. A.S., C.R., K.W., R.P. and S.W. developed the fabrication process and methodology for the PlasticARM FlexIC. All authors contributed to analysis of the data generated in the development of PlasticARM. E.O., J.B., J.K., J.M., C.R., R.P. and S.W. wrote the paper.
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Peer review information Nature thanks Zili Yu and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Extended data figures and tables
Extended Data Fig. 1 Evolution of the standard cell architecture.
The figure shows the evolution of the standard cell library from left to right. It starts with a 1-μm channel length library, and then moves to an 0.8 μm channel length with different sheet resistances. The far right panel shows the final library that is used to implement the PlasticARM FlexIC. VDD, supply voltage; VSS, ground; CONT, electrical contact between the source–drain layer and the next metal layer; VIA, electrical contact between routing layers.
Extended Data Fig. 2 Layouts and transfer characteristics of buffers.
a, Layouts of X4 buffers with resistive pull-up (BUF_X4) are shown on the left and layouts of X4 buffers with active transistor pull-up (BUF_X4M) are shown on the right. b, Simulated responses including parasitic capacitance and resistance extracted from the layout. The maximum capacitive load of BUF_X4 is 4.8 pF, based on the data from the liberty file at the typical corner. Buffers with active pull-up can drive much higher loads and consume less static power than their resistive load counterparts at the expense of area increase and reduced output voltage range due to a drop in VDS (the voltage between the drain and source electrodes) across the pull-up transistor. For X4 cells the average static power consumption reduces by 60%, area increases by 43% and the VDS drop is 0.2 V.
Extended Data Fig. 3 Simulation of the PlasticARM RTL.
a, GPIO toggles are shown when data are correct in all three tests. b, GPIO toggles are shown when data read from the ROM is incorrect. The simulation was run with a 20-kHz clock frequency.
Extended Data Fig. 4 PlasticARM timing measurements of all three tests.
a, Waveform showing the functionality of PlasticARM that correctly matches the RTL simulation. b, Magnified views of GPIO input pin (I_GPIO[1]) changing from logic 0 to logic 1. c, GPIO output pin (O_GPIO[0]) changing from logic 0 to logic 1, marking an input that was held HIGH for about 1 s. The experiment was carried out with a 20-kHz clock frequency.
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Biggs, J., Myers, J., Kufel, J. et al. A natively flexible 32-bit Arm microprocessor. Nature 595, 532–536 (2021). https://doi.org/10.1038/s41586-021-03625-w
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DOI: https://doi.org/10.1038/s41586-021-03625-w
