SEEQC Develops Digital Interface for Real-Time Quantum-Classical Integration with NVIDIA-Powered Error Correction

Insider Brief

• SEEQC and NVIDIA have demonstrated the first end-to-end fully digital quantum-classical interface, enabling direct chip-to-chip communication between a quantum processor and a GPU for ultra-low latency quantum error correction.
• Leveraging SEEQC’s Single Flux Quantum (SFQ) technology, the interface reduces error correction latency to microseconds while using 1000x less bandwidth, addressing a key bottleneck in scaling quantum computing.
• This collaboration advances heterogeneous computing by integrating quantum and classical systems, with SEEQC’s digital interface designed for compatibility with NVIDIA’s CUDA-Q platform to support scalable fault-tolerant quantum computing.

PRESS RELEASE — In a world-first, SEEQC and NVIDIA have completed an end-to-end fully digital quantum-classical interface protocol demo between a QPU and GPU. This is a key milestone towards delivering the first fully digital chip-to-chip interface for connecting quantum processors with a classical GPU to be used for ultra-low latency and bandwidth-efficient quantum error correction. The news has been announced as part of a fireside chat hosted by NVIDIA CEO Jensen Huang and including SEEQC co-founder and CEO John Levy at the first NVIDIA Quantum Day. 

SEEQC’s interface is designed around taking advantage of its Single Flux Quantum (SFQ) technology’s ultra-fast clock speeds and on-Quantum Processor digitization to eliminate bandwidth bottlenecks, reduce latency and create an optimal digital link to NVIDIA GPUs. The interface completed error correction with just microsecond round-trip latency, while using 1000x less bandwidth – taking requirements for scalable quantum error correction from terabits down to gigabits per second, removing a critical bottleneck for scaling quantum computers. SEEQC’s end-to-end quantum error correction demo leveraged the power of NVIDIA accelerated computing for decoding, demonstrating the importance of integrating quantum and classical computing for large-scale quantum devices.

While past breakthroughs have connected QPUs to the cloud or within data centres – making error correction possible, though with long lag – no company has ever built a direct chip-to-chip digital interface designed for ultra-low latency error correction with such low bandwidth requirements. This is only possible because SEEQC’s SFQ controller integrates quantum and classical computing functions onto a single digital chip. This offers an alternative to the common approaches to control systems for quantum error correction – which send control signals through long cables from cryogenically-cooled qubits to room-temperature electronics. This universal chip-based interface, when integrated with any GPU, forms a fully integrated full-stack quantum/classical processor that operates at the same temperatures as qubits to offer real-time digital readout and control via SEEQC’s PRISM firmware and software.

John Levy, SEEQC co-founder and CEO said: “Quantum and classical computing have often been seen as competing forces. It’s even shaped how these systems are designed – built separately, connected inefficiently, and unable to fully lean on each other’s strengths. Our technology and our latest breakthrough with NVIDIA changes this. By creating a direct, fully digital link between quantum processors and GPUs, we’re unlocking the true power of both in a way that makes the whole greater than the sum of its parts.”

Sam Stanwyck, Group Product Manager for Quantum Computing at NVIDIA said: “Tightly integrating quantum hardware and AI supercomputing is critical for the quantum error correction that enables useful large-scale quantum computing. Our work with SEEQC is helping to close the gap between these technologies and bring reliable quantum applications closer to reality.”

This demonstration validates SEEQC’s digital-first approach and is the first step in an ongoing collaboration with NVIDIA. For this stage, the interface was built using PCIe, the current high-speed data transfer standard. This will act as a reference for a future generation interface which will introduce custom on-GPU protocol integration to further enhance efficiency, ultimately scaling to million-qubit systems.

Towards heterogeneous computing

Beyond a company-wide milestone, this breakthrough is also a major milestone toward heterogeneous computing – where quantum and classical systems work together seamlessly, unlocking new possibilities that neither can achieve alone.

By design, SEEQC’s digital interface is compatible with NVIDIA CUDA-Q platform, which  is built to enable simple, concurrent access to quantum and classical hardware, allowing quantum processors to work alongside GPUs and CPUs for developing real-world applications. Longer-term, SEEQC’s work integrating NVIDIA’s accelerated computing paves the way for fault-tolerant, truly scalable quantum computing.