Efficient implementation of single particle Hamiltonians in exponentially reduced qubit space

Quantum 10, 2099 (2026).

https://doi.org/10.22331/q-2026-05-08-2099

Current and near-term quantum hardware is constrained by limited qubit counts, circuit depth, and the high cost of repeated measurements. We address these challenges for solid-state Hamiltonians by introducing a logarithmic-qubit encoding that maps a system with $N$ physical sites onto only $lceil log_2 N rceil$ qubits while maintaining a clear correspondence with the underlying physical model. Within this reduced register, we construct a compatible variational circuit and a Gray-code-inspired measurement strategy whose number of global settings grows only logarithmically with system size. To quantify the overall hardware load, we introduce a volumetric efficiency metric that combines the number of qubits, circuit depth, and the number of measurement settings into a single measure, expressing the overall computation costs. Using this metric, we show that the total space–time sampling volume required in a variational loop can be reduced dramatically from $N^2$ to $(log N)^3$ for a hardware-efficient ansatz, allowing an exponential reduction in time and size of the quantum hardware. These results demonstrate that large, structured solid-state Hamiltonians can be simulated on substantially smaller quantum registers with controlled sampling overhead and manageable circuit complexity, extending the reach of variational quantum algorithms on near-term devices.