NTT Unveils First Quantum Computing Architecture Separating Memory and Processor

Insider Brief

• Researchers developed a fault-tolerant quantum computing architecture that separates memory and processing, improving portability and reducing quantum resource requirements by about 40%.
• The load-store architecture enables efficient memory utilization and program portability by abstracting data exchange into “load” and “store” operations, addressing scalability and compatibility challenges.
• The approach achieves near 100% memory efficiency and limits computation time increases to 5%, potentially accelerating the practical application of quantum computing.

PRESS RELEASE — Researchers with NTT Corporation (NTT), The University of Tokyo, Kyushu University and RIKEN announced the development of a new, fault-tolerant quantum computing architecture that separates memory and processor, improving portability and efficiency. By applying a load-store-type structure, the proposed design is expected to reduce quantum resource requirements by approximately 40%, overcoming the scaling, memory utilization and portability issues of conventional, quantum-circuit-based designs.

These findings, entitled, “LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing” are being presented at the 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA-31) to be held from March 1, 2025.

The Problems of Conventional Quantum Computer Design

Conventional quantum computer designs apply quantum circuits whereby programs are expressed and executed from computable registers, where the quantum data is stored. This approach presents a challenge for scaling up as the computer must be expanded while maintaining the ability to perform arbitrary basic operations on all data, no matter where the data is stored on the device. Additionally, these programs are optimized specifically for the size of the devices and the error correction method, making it difficult to port executable files to computers even with slightly different configurations.

For example, in the mainstream method for fault-tolerant quantum computation using two-dimensionally aligned qubits, computation is performed using blocks encoded with quantum error-correcting codes (called “surface codes”) as data units. To allow all code blocks to perform arbitrary calculations based on quantum circuits, an additional code block must be placed next to the cell holding all data. Since these auxiliary cells cannot be used to hold data, only between 44% and 67% of a quantum device is actually used for calculations.

NTT and Collaborators Apply a Modern Approach to Next-Generation Computing

In this study, researchers applied the design concept of the load-store-type architecture used in modern computers to quantum computing. In a load-store architecture, the device is divided into a memory and a processor to perform calculations. By exchanging data using two abstracted instructions, “load” and “store,” programs can be built in a portable way that does not depend on specific processor or memory device structures. Additionally, the memory is only required to hold data, allowing for high memory utilization.

Load-store computation is often associated with an increase in computation time due to the limited memory bandwidth between memory and computation spaces. By proposing new quantum memory methods such as row access type and point access type, this study shows that 100% memory efficiency can be achieved asymptotically, and approximately 90% efficiency can be achieved in practical cases. Moreover, this approach successfully reduced the computation time increase to approximately 5% compared to a computer that can perform calculations in the entire area of the computer.

Pursuing Practical Quantum Computing Design

Researchers expect these findings to enable the highly efficient utilization of quantum hardware, significantly accelerating the practical application of quantum computation. Additionally, the high program portability of this approach helps to ensure the compatibility between hardware advancement, error correction methods at the lower layer and the development of technology at the higher layer, such as programming languages and compilation optimization. The findings will facilitate the promotion of parallel advanced research in large-scale quantum computer development.

The significance of this study lies in demonstrating that the concepts of load, store and cache—fundamental in conventional computer architecture—are also effective in the quantum computer field. It is anticipated that this work will catalyze active research and development across both computer architecture and quantum computers, ultimately establishing the foundational design of practical quantum computation.

Contributing Authors

Takumi Kobori (Department of Physics, The University of Tokyo), Yasunari Suzuki (NTT Computer and Data Science Laboratories), Yosuke Ueno (RIKEN Center for Quantum Computing), Teruo Tanimoto (Kyushu University), Synge Todo (Department of Physics, The University of Tokyo) Yuuki Tokunaga (NTT Computer and Data Science Laboratories).

About NTT

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